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pub. # 22829 rev : c amendment : /0 issue date: december 1999 intelligent access ? voice solutions am79d2251 dual intelligent subscriber line audio-processing circuit (islac ? ) distinctive characteristics high performance digital signal processor provides programmable control of all major linecard functions ? 32 and 24 kb/s adpcm to g726, as well as a-law/ -law and linear codec ? transmit and receive gain ? two-wire ac impedance ? transhybrid balance ? equalization ? dc loop feeding ? smooth or abrupt polarity reversal ? loop supervision ? off-hook debounce circuit ? ground-key and ring-trip filters ? ringing generation and control ? adaptive hybrid balance ? line and circuit testing ? tone generation ? metering generation at 12 khz and 16 khz ? envelope shaping and level control selectable pcm/mpi or gci digital interfaces ? supports most available master clock frequencies from 512 khz to 8.196 mhz 0 to 70c commercial operation ?? 40 c to 85 c extended temperature range available +3.3 v dc operation exceeds lssgr and itu requirements supports external ringing with on-chip ring-trip circuit ? automatic or manual ring-trip modes dtmf detection according to q.24 2100 hz modem tone detection according to v.25 block diagram rc networks and protection a1 b1 a2 b2 dual islac islic islic ld1 vref 7 agnd1 agnd2 rref batp bath ring-trip sense resistors 5 5 batl rshb rslb rspb vcca 4 vccd dgnd1 dgnd2 tsca/g dra/dd dxa/du dclk/s0 pclk/fs mclk fs/dcl cs/rst dio/s1 int 3 p1-p3 7 ld2
2 am79d2251 table of contents distinctive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 distinctive characteristics of the intelligent access ? voice chipset . . . . . . . . . . . . . . . . . . . . . . 3 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 connection diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 linecard parts list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 intelligent access ? voice chipsets environmental ranges . . . . . . . . . . . . . . . . . . . . 14 electrical maximum ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 performance specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 intelligent access ? voice chipsets system target specifications . . . . . . . . . . . . . . . . . . . 15 dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 transmission and signaling specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 transmit and receive paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 attenuation distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 group delay distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 single frequency distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 intermodulation distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 gain linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 total distortion including quantizing distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 overload compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 discrimination against out-of-band input signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 spurious out-of-band signals at the analog output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 pcm switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 pcm interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 master clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 pcm switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 gci timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0 gci waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 44-pin plcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 44-pin tqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 revision summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 revision a to revision b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 revision b to revision c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
am79d2251 3 the dual islac ? device, in combination with an islic ? device, implements a two channel universal telephone line interface. this enables the design of a single, low cost, high performance, fully software programmable line interface for multiple country applications worldwide. all ac, dc, and signaling parameters are fully programmable via microprocessor or gci interfaces. additionally, the dual islac device has integrated self-test and line-test capabilities to resolve faults to the line or line circuit. the integrated test capability is crucial for remote applications where dedicated test hardware is not cost effective. distinctive characteristics of the intelligent access ? voice chipset performs all battery feed, ringing, signaling, hybrid and test (borscht) functions two chip solution supports high density, multi- channel architecture single hardware design meets multiple country requirements through software programming of: ? ringing waveform and frequency ? dc loop-feed characteristics and current-limit ? loop-supervision detection thresholds ? off-hook debounce circuit ? ground-key and ring-trip filters ? off-hook detect de-bounce interval ? two-wire ac impedance ? transhybrid balance ? transmit and receive gains ? equalization ? digital i/o pins ? a-law/-law and linear selection supports internal and external battery-backed ringing ? self-contained ringing generation and control ? supports external ringing generator and ring relay ? ring relay operation synchronized to zero crossings of ringing voltage and current ? integrated ring-trip filter and software enabled manual or automatic ring-trip mode supports metering generation with envelope shaping smooth or abrupt polarity reversal adaptive transhybrid balance ? continuous or adapt and freeze supports both loop-start and ground-start signaling exceeds lssgr and ccitt central office requirements selectable pcm or gci interface ? supports most available master clock frequencies from 512 khz to 8.192 mhz on-hook transmission power/service denial mode line-feed characteristics independent of battery voltage only 5 v, 3.3 v and battery supplies needed low idle-power per line linear power-feed with intelligent power- management feature compatible with inexpensive protection networks; accommodates low-tolerance fuse resistors while maintaining longitudinal balance monitors two-wire interface voltages and currents for subscriber line diagnostics built-in voice-path test modes power-cross, fault, and foreign voltage detection integrated line-test features ? leakage ? line and ringer capacitance ? loop resistance integrated self-test features ? echo gain, distortion, and noise 0 to 70 c commercial operation ?? 40 c to 85 c extended temperature range available small physical size up to three relay drivers per islic ? device ? configurable as test load switches
4 am79d2251 figure 1. dual islac ? block diagram clock and reference circuits pcm and gci interface and time slot assigner digital signal processor gci control logic and microprocessor interface islic control logic common external sense inputs mclk iref vref fs/dcl pclk/fs dxa/du dra/dd tsca/g dclk/s0 dio/s1 int cs/rst xsc shb slb spb ch 1 converter block vhl1 vlb1 vout1 vilg1 vimt1 vsab1 vini1 xsb1 ch 2 converter block vhl2 vlb2 vout2 vilg2 vimt2 vsab2 vini2 xsb2 p1 ld2 ld1 p2 p3
am79d2251 5 ordering information amd standard products are available in several packages and operating ranges. the ordering number (valid combination) is formed by a combination of the elements below. two islic devices need to be used with this part. j valid combinations valid combinations list configurations planned to be supported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations, and to check on newly released valid combinations. device name/description am79d2251 advanced dual intelligent subscriber line audio- processing circuit temperature range c= commercial (0 c to +70 c) package type j = 44-pin plastic leaded chip carrier (pl044) v = 44-pin thin plastic quad flat pack (pqt044) am79d2251 c valid combinations am79d2251 jc am79d2251 vc
6 am79d2251 connection diagrams figure 2. 44-pin plcc connection diagram figure 3. 44-pin tqfp connection diagram dual islac 44-pin plcc 1 2 3 4 54440 41 42 43 6 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 15 16 17 7 8 9 10 11 12 13 14 ld2 p3 vcca2 dgnd1 spb vhl2 vin2 vout2 vsab2 vilg2 agnd1 cs/rst vcca1 dgnd2 vilg1 vsab1 vhl1 vin1 vout1 ld1 dclk/s0 agnd2 vref iref vlb1 xsb1 vimt1 xsc vimt2 vlb2 xsb2 slb shb vccd mclk pclk/fs tsca/g dio/s1 p1 p2 dxa/du dra/dd fs/dcl int/s2 dual islac 44-pin tqfp 22 21 20 19 18 17 16 15 14 13 12 23 24 25 26 27 28 29 30 31 32 33 1 2 3 4 5 6 7 8 9 10 11 34 35 36 37 38 39 40 41 42 43 44 vref iref vlb1 xsb1 vimt1 xsc vimt2 vlb2 xsb2 slb shb ld2 p3 vcca2 dgnd1 spb vhl2 vin2 vout2 vsab2 vilg2 agnd1 cs/rst vcca1 dgnd2 vilg1 vsab1 vhl1 vin1 vout1 ld1 dclk/s0 agnd2 vccd mclk pclk/fs tsca/g dio/s1 p1 p2 dxa/du dra/dd fs/dcl int/s2
am79d2251 7 pin descriptions pin pin name i/o description agnd1, agnd2 analog ground o analog circuitry ground returns dclk/s0 data clock/gci address strap 0 i provides data control for mpi interface control. for gci operation, this pin is device address bit 0. 5 v tolerant. dgnd1 ? dgnd2 digital ground digital ground returns dio/s1 data i/o/gci address strap 1 i/o for pcm backplane operation, control data is serially written into and read out of the islac device via the dio pin with the msb first. the data clock (dclk) determines the data rate. dio is high impedance except when data is being transmitted from the islac device under control of cs /rst . for gci operation, this pin is device address bit 1. 5 v tolerant. dra/dd rx path a backplane data/ gci data downstream, receive path b backplane data i for the pcm highway, the receive pcm data is input serially through the dra ports. the data input is received every 125 s and is shifted in, msb first, in 8-bit pcm or 16-bit linear bursts at the pclk rate. the receive port can receive information for direct control of the islic device. this mode is selected in device configuration register 2 (rtsen = 1, rtsmd = 1). when selected, this data is received in an independently programmable timeslot from the pcm data. for the gci mode, downstream receive and control data is accepted on this pin. 5 v tolerant. dxa/du tx path a backplane data/gci data upstream, tx path b backplane data o for the pcm highway, the transmit pcm data is transmitted serially through the dxa port. the transmission data output is available every 125 s and is shifted out, msb first, in 8-bit pcm or 16-bit linear bursts at the pclk rate. dxa is high impedance between bursts and while the device is in the inactive mode. can also select a mode (rtsen = 1, rtsmd = 1 or 0 in device configuration register 2) that transmits the signaling register msb contents first, in an independently programmable timeslot from the pcm data. this data is transmitted in all modes except disconnect. for the gci mode, upstream transmit and signaling data is transferred on this pin. 5 v tolerant. fs/dcl frame sync/gci downstream clock i for pcm operation, pin is frame sync. pcm operation is selected by the presence of an 8 khz frame sync signal on this pin in conjunction with the pclk on the pclk/fs pin (see below). this 8 khz pulse identifies the beginning of a frame. the islac device references individual timeslots with respect to this input, which must be synchronized to pclk. gci operation is selected by the presence of the downstream clock dcl, on this pin in conjunction with the presence of a fs on the pclk/fs pin. in gci mode, the rate at which data is shifted into or out of the pcm ports is a derivative of this dcl clock as selected in device configuration register 1. 5 v tolerant. int/s2 interrupt/gci address strap 2 o for pcm operation, when a subscriber line requires service, this pin goes to a logic 0 to interrupt a higher level processor. several registers work together to control operation of the interrupt: signaling and global interrupt registers with their associated mask registers, and the interrupt register. see the description at configuration register 6 (mask) for operation. logic drive is selectable between open drain and ttl-compatible outputs. the s2 function is only available on the dual islac device. for gci operation, it is the device address bit 2. iref current reference i external resistor (rref) connected between this pin and analog ground generates an accurate, on-chip reference current for the a/d's and d/a's on the islac chip. ld1 ? ld2 register load o the ld pins output 3-level voltages. when ldn is a logic 0, the destination of the code on p1 ? p3 is the relay control latches in the islic control register. when ldn is a logic 1, the destination of p1 ? p3 is the mode control latches. ldn is driven to vref when the contents of the islic control register must not change. mclk master clock i for pcm backplane operation, a dsp master clock connects here. a signal is required only for pcm backplane operation when pclk is not used as the master clock. mclk can be a wide variety of frequencies. upon initialization the mclk input is disabled, and relevant circuitry is driven by a connection to pclk. the mclk connection may be re-established under user control. 5 v tolerant. pclk/fs pcm clock/frame sync i for pcm operation, this is pcm clock. pcm operation is selected by the presence of a pclk signal on this pin in conjunction with the fs on the fs/dcl pin (see below). for pcm backplane operation, connect a data clock, which determines the rate at which pcm data is serially shifted into or out of the pcm ports. pclk can be any multiple of the fs frequency. the minimum clock frequency for linear/ companded data plus signaling data is 256 khz. for gci operation, this pin is frame sync. the fs signal is an 8 khz pulse that identifies the beginning of a frame. the islac device references individual timeslots with respect to this input, which must be synchronized to dcl. 5 v tolerant. p1 ? p3 islic control o control the operating modes of the two islic devices connected to the dual islac device.
8 am79d2251 cs /rst chip select/reset i for pcm backplane operation, a logic low on this pin for 15 or more dclk cycles resets the sequential logic in the islac device into a known mode. a logic low placed on this pin for less than 15 dclk cycles is a chip select and enables serial data transmission into or out of the dio port. for gci operation, a logic low on this pin ? for 1 ms or longer ? resets the sequential logic into a known mode. see table 2-4 in the technical reference for details. 5 v tolerant. shb, slb, spb battery sense i resistors that sense the high, low and positive battery voltages connect here. if only one negative battery is used, connect both resistors at the supply. if the positive battery is not used, leave the pin unconnected. these pins are current inputs whose voltage is held at vref. tsca /g, timeslot control a/gci mode, time slot control b o (pcm) i (gci) for pcm backplane operation, tsca is active low when pcm data is output on the dxa pin. the outputs are open-drain and are normally inactive (high impedance). pull-up loads should be connected to vccd. when gci mode is selected, one of two gci modes may be selected by connecting tsca /g to dgnd or vccd. vsab1 ? vsab2 loop voltage sense i connect to the vsab pins of two islic devices. vcca1 ? vcca2 power supply +3.3 vdc supplies to the analog sections in each of the two channels. vccd power supply +3.3 vdc supply to all digital sections. vref analog reference o this pin provides a 1.4 v, single-ended reference to the two islic devices to which the islac device is connected. vhl1 ? vhl2 high level d/a o high-level loop control voltages on these pins are used to control dc-feed, internal ringing, metering and polarity reversal for each islic device. vin1 ? vin2 tx analog i analog transmit signals (vtx) from each islic device connect to these pins. the islac device converts these signals to digital words and processes them. after processing, they are multiplexed into serial time slots and sent out of the dxa/du pin. vlb1 ? vlb2 longitudinal reference o normally connected to vcca internally. they supply longitudinal reference voltages to the islic devices during certain test procedures. these outputs are connected internally to vcca during islic active, standby, ringing, and disconnect modes. during test modes, it can be connected to the receive d/a. vimt1 ? vimt2, vilg1 ? vilg2 sense i the imt and ilg pins of two islic devices connect to the vimt1 ? vimt4 and vilg1 ? vilg4 pins of the islac chip. these pins are voltage inputs referenced to vref. they require external resistors connected between each pin and vref to convert imtn and ilgn into voltages. vout1 ? vout2 rx analog o the islac device extracts and processes voice data from time slots on dra/dd serial data port. after processing, the islac device converts the voice data to analog signals that are sent out of these pins to each respective islic device. xsb1 ? xsb2 external sense i external resistors connect here that sense an external voltage. in a linecard with external ringing, they are used to sense the voltage at the line side of the ring-feed resistor. these pins are current inputs whose voltage is held at vref. an internal resistor converts currents flowing in these pins into voltages to be sampled by the a/d. xsc common external sense i an external resistor connects here that senses a common reference for external voltages sensed by resistors connected to xsb1 ? xsb4. this pin is a current input whose voltage is held at vref. an internal resistor converts current flowing in this pin into a voltage to be sampled by the a/d. this pin is intended for sensing external ringer supply voltages. however, it can also be used to sense other test points when internal ringing is used. pin pin name i/o description
am79d2251 9 general description the intelligent access ? voice chipsets integrate all functions of the subscriber line for two subscriber lines. one or more of two chip types are used to implement the linecard; an islic device and a dual islac device. these provide the following basic functions: 1. the islic device: a high voltage, bipolar ic that drives the subscriber line, maintains longitudinal balance and senses line conditions. 2. the dual islac device: a low voltage cmos ic that provides conversion and dsp functions for 2 channels. complete schematics of linecards using the intelligent access voice chipsets for internal and external ringing are shown in figure 4 and figure 5. the islic device uses reliable, bipolar technology to provide the power necessary to drive a wide variety of subscriber lines. it can be programmed by the islac device to operate in eight different modes that control power consumption and signaling modes. this enables it to have full control over the subscriber loop. the islic device is customized to be used exclusively with the islac device as part of a multiple-line chipset. the islic device requires only +5 v power and the battery supplies for its operation. the islic device implements a linear loop-current feeding method with the enhancement of intelligent thermal management in a controlled manner. this limits the amount of power dissipated on the islic chip by dissipating excess power in external resistors. each islac device contains high-performance codec circuits that provide a/d and d/a conversion for voice (codec), dc-feed and supervision signals for two subscriber channels. the islac device contains a dsp core that handles signaling, dc-feed, supervision and line diagnostics for both channels. the dsp core selectively interfaces with three types of backplanes: standard pcm/mpi standard gci modified gci with a single analog line per gci channel the intelligent access voice chipset provides a complete software configurable solution to the borscht functions as well as complete programmable control over subscriber line dc-feed characteristics, such as current limit and feed resistance. in addition, these chipsets provide system level solutions for the loop supervisory functions and metering. in total, they provide a programmable solution that can satisfy worldwide linecard requirements by software configuration. software programmed filter coefficients, dc-feed data and supervision data are easily calculated with the winslac ? software. this pc software is provided free of charge. it allows the designer to enter a description of system requirements. winslac then computes the necessary coefficients and plots the predicted system results. the islic interface unit inside the islac device processes information regarding the line voltages, loop currents and battery voltage levels. these inputs allow the islac device to place several key islic performance parameters under software control.
10 am79d2251 the main functions that can be observed and/or controlled through the islac backplane interface are: dc-feed characteristics ground-key detection off-hook detection dtmf detection modem tone (2100 hz) detection metering signal longitudinal operating point subscriber line voltage and currents ring-trip detection abrupt and smooth battery reversal subscriber line matching ringing generation sophisticated line and circuit tests to accomplish these functions, the islic device collects the following information and feeds it, in analog form, to the islac device: the metallic (imt) and longitudinal (ilg) loop currents the ac (vtx) and dc (vsab) loop voltage the outputs supplied by the islac device to the islic device are then: a voltage (vhli) that provides control for the following high-level islic device outputs: ? dc loop current ? internal ringing signal ? 12 or 16 khz metering signal a low-level voltage proportional to the voice signal (vouti) a voltage that controls longitudinal offset for test purposes (vlbi) the islac device performs the codec and filter functions associated with the four-wire section of the subscriber line circuitry in a digital switch. these functions involve converting an analog voice signal into digital pcm samples and converting digital pcm samples back into an analog signal. during conversion, digital filters are used to band-limit the voice signals. the user-programmable filters set the receive and transmit gain, perform the transhybrid balancing function, permit adjustment of the two-wire termination impedance and provide frequency attenuation adjustment (equalization) of the receive and transmit paths. adaptive transhybrid balancing is also included. all programmable digital filter coefficients can be calculated using winslac software. the pcm codes can be either 16-bit linear two ? s-complement or 8-bit companded a-law or -law, with the further option of 32 or 24 kb/s adpcm compression. besides the codec functions, the intelligent access voice chipset provides all the sensing, feedback, and clocking necessary to completely control islic device functions with programmable parameters. system-level parameters under programmable control include active loop current limits, feed resistance, and feed mode voltages. the islac device supplies complete mode control to the islic device using the control bus (p1-p3) and tri-level load signal (ldi). the intelligent access voice chipset provides extensive loop supervision capability including off-hook, dtmf, ring-trip and ground-key detection. detection thresholds for these functions are programmable. a programmable debounce timer is available that eliminates false detection due to contact bounce. for subscriber line diagnostics, ac and dc line conditions can be monitored using built in test tools. measured parameters can be compared to programmed threshold levels to set a pass/fail bit. the user can choose to send the actual pcm measurement data directly to a higher level processor by way of the voice channel. both longitudinal and metallic resistance and capacitance can be measured, which allows leakage resistance, line capacitance, and telephones to be identified.
am79d2251 11 figure 4. internal ringing linecard schematic rfai rfbi rsai rsbi a b u3 dhi bath batl u1 am79r241 p1 p2 p3 ld sa sb ad bd vbh vbl tmp tmn rsn vlb imt ilg vtx vref vsab gnd +5 v vcc cbatli cbathi * css required for > 2.2 vrms metering ** connections shown for one channel *** dt2i diode is optional - should be connected if there is a chance that this chip may be replaced by am79r251. dli rmgli rmgpi tms bgnd r2 rye r3 r1 bath hpa hpb rtestli chpi cssi rrxi rmti vref rlgi vref u2 islac vref vilgi vimti vlbi vsabi vini vouti back plane ldi p1 p2 p3 dgnd vcca vccd shb slb bath batl iref agnd vcc +3.3vdc rshb rslb rref cref 3.3 v cadi cbdi rsvd rsvd rti d1 d2 u4 cs rtestmi dt1i dt2i *** spb rhlai vhli rhlbi rhlci rhldi vref chldi chlbi
12 am79d2251 figure 5. external ringing linecard schematic rfai rfbi rsai rsbi rrxi a b dhi bath batl u1 am79231 p1 p2 p3 ld rsn vlb imt ilg vtx vref vsab gnd +5 v vcc cbatli cbathi * css required for > 2.2 vrms metering ** connections shown for one channel *** dt2i is optional - should be put if there is a chance that this chip may be replaced by am79r251. dli rmgli rmgpi rmti vref rlgi vref rhlai bath cs 45 8 1 2 u5 6 7 rtestmi dt1i rtestli rsrbi rsrc rgfdli ring bus kri kri(a) cadi cbdi chpi cssi u2 islac vref vilgi vimti vlbi vsabi vini vhli vouti back plane ldi p1 p2 p3 dgnd agnd vcca vccd rshb rslb shb slb bath batl rref iref xsbi xsc vcc +3.3 vdc +5 v kri spb rsvd cref 3.3 v rti (b) dt2i *** rhlbi rhlci rhldi vref chldi chlbi sa sb ad bd vbh vbl tmp tmn tms bgnd r2h rye r3h r1 hpa hpb rsvd2
am79d2251 13 linecard parts list the following list defines the parts and part values required to meet target specification limits for channel i of the linecard (i = 1, 2) notes: 1. value can be adjusted to suit application. 2. can be looser for relaxed ring-trip requirements. 1% match (each resistor 1%) gives 1.275 ma uncertainty in ringing current sensing. 3. required for metering > 2.5 vrms, otherwise may be omitted. 4. dt2i is optional - should be put if there is a chance that this chip may be replaced by am79r251. item type value tol. rating comments u1 am79r241 islic device u2 am79x22xx islac device u3, u4 p1001sc 100 v teccor battrax protector u5 tisp61089 80 v transient voltage suppresser, power innovations d1, d2 diode 1 a 100 v dhi, dli, dt1i, dt2i 4 diode 100 ma 100 v 50 ns rfai, rfbi resistor 50 ? 2% 2 w fusible ptc protection resistors rsai, rsbi resistor 200 k ? 2% 1/4 w sense resistors rti resistor 80.6 k ? 1% 1/8 w rrxi resistor 100 k ? 1% 1/8 w rref resistor 69.8 k ? 1% 1/8 w current reference rmgli, rmgpi resistor 1 k ? 5% 1 w thermal management resistors rshb, rslb resistor 750 k ? 1% 1/8 w rhlai resistor 40.2 k ? 1% 1/10 w rhlbi resistor 4.32 k ? 1% 1/10 w rhlci resistor 2.87 k ? 1% 1/10 w rhldi resistor 2.87 k ? 1% 1/10 w chlbi capacitor 3.3 nf 10 % 10 v not polarized chldi capacitor 0.82 f 10 % 10 v ceramic rmti resistor 3.01 k ? 1% 1/8 w rlgi resistor 6.04 k ? 1% 1/8 w rtestmi resistor 2 k ? 1% 1 w metallic test rtestli resistor 2 k ? 1% 1 w longitudinal test cadi, cbdi 1 capacitor 22 nf 10% 100 v ceramic, not voltage sensitive cbathi, cbatli capacitor 100 nf 20% 100 v ceramic chpi capacitor 22 nf 20% 100 v ceramic csi 1 capacitor 100 nf 20% 100 v protector speed up capacitor cssi 3 capacitor 56 pf 5% 100 v ceramic components for external ringing rgfdi resistor 510 ? 2% 2 w 1.2 w typ rsrbi, rsrc resistor 750 k ? 2% 1/4 w matched to within 0.2% for initial tolerance and 0 to 70 c ambient temperature range. 2 17 mw typ kri relay 5 v coil dpdt
14 am79d2251 electrical characteristics power dissipation absolute maximum ratings stresses greater than those listed under absolute maximum ratings can cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods can affect device reliability. operating ranges operating ranges define those limits over which the functionality of the device is guaranteed by 100 percent production testing. specifications outside of the 0 to 70 c range ( ? 40 to 85 c) are guaranteed through characterization and sample-lot testing production devices at the temperature extremes. intelligent access ? voice chipsets environmental ranges electrical maximum ranges description test conditions min typ max unit dual islac power dissipation one channel activated tbd tbd mw all channels active tbd tbd all channels inactive tbd storage temperature ? 60 c t a +125 c ambient temperature, under bias ? 40 c t a +85 c ambient relative humidity (non condensing) 5 to 100% v cca with respect to dgnd ? 0.4 v to + 3.47 v v ccd with respect to dgnd ? 0.4 v to + 3.47 v v in with respect to dgnd ? 0.4 v to vcca + 0.4 v 5 v tolerant pins ? 0.4 to vcc + 2.25 or 5.25 v, whichever is less agnd dgnd 0.4 v latch up immunity (any pin) 100 ma any other pin with respect to dgnd ? 0.4 v to v cc ambient temperature ? 40 to +85 c commercial ambient relative humidity 15 to 85% analog supply v cca +3.3 v 5% digital supply v ccd +3.3 v 5% dgnd 0 v agnd dgnd 50 mv
am79d2251 15 performance specifications the performance targets defined in this section are for the entire linecard comprised of both chips in the intelligent access voice chipsets unless otherwise noted. specifications for the individual chips in the set will be published separately (see note 1). t a = 0 to 70 c unless otherwise noted. intelligent access ? voice chipsets system target specifications notes: 1. not tested or partially-tested in production. 2. these numbers are only valid when an islic device operates with an islac device, because the islac generates the anti-sat feed characteristic. when the intelligent access voice chipsets operate in the normal feed region, the performance is controlled by the islic device. see appropriate islic data sheet for specific psrr. item condition min typ max unit note peak ringing voltage active ringing mode, rload = 1500 ? , vbh = 80 v 70 v output impedance during internal ringing active ringing mode, dual islac generating internal ringing 200 ? sinusoidal ringing thd active ringing mode, rload = 1500 ? , vbh = 80 v, islac generating internal sinusoidal ringing 2% psrr (vbh, vbl) loop open, in anti-sat f = 50 hz f = 200 to 3400 hz 2 12 db 1, 2
16 am79d2251 dc specifications no. item condition min typ max unit note 1 input low voltage, all other digital inputs ? 0.05 ? 0.50 1.36 v 0.80 v v 2 input high voltage, all other digital inputs 2.36 2.0 vcc+0.4 5.25 4 input leakage current all digital inputs except mclk mclk ? 10 ? 120 +10 +180 a 5 input hysteresis (pclk/fs, fs/dcl, mclk, dio, dra) 0.15 0.225 0.3 v2 6 ternary output voltages, ld1 ? 2 high voltage low voltage output current iout = 200 a iout = 2 ma mid level vcc ? 0.45 ? ? 10 ? 0.4 +10 v v a 7 output low voltage (dxa/du, dio, int , tsca ) iol = 2 ma 0.4 v 8 output low voltage (int , tsca ) iol = 10 ma 1.0 9 output high voltage (all digital outputs except int in open drain mode and tsca ) ioh = 400 a vcc ? 0.4 10 input leakage current (vin1 ? 2, vsab1 ? 2, vilg1 ? 2, vimt1 ? 2) tbd a 11 input leakage current ( vsab1 ? 2) tbd a 12 input voltage (vin1 ? 2) -law a-law 3.205 dbm0 3.14 dbm0 to insertion loss in adc vref ? 1.02 vref +1.02 v 13 input voltage (vsab 1 ? 2 or vimt1 ? 2 or vilg1 ? 2) |vov ? vref| where vov is input overload voltage 0.99 1.02 1.05 14 offset voltage allowed on vin1 ? 2 ? 50 +50 mv 9 15 vhl output offset voltage 16 vout1 ? 2 offset voltage disn off disn on ? 40 ? 80 +40 +80 17 output voltage, vref load current = 0 to 10 ma source or sink 1.4 v 18 capacitance load on vref or vout1 ? 2 200 pf 2 19 output drive current, vout1 ? 2 or vlb1 ? 2 source or sink ? 1+1ma2 20 output leakage current vout1 ? 2 or vlb1 ? 2 tbd ma 21 maximum output voltage on vout |vout ? vref| with peak digital input 0.99 1.02 1.05 v 9 22 vlb1 ? 2 operating voltage source current < 250 a or sink current < 25 a. vref ? 1.02 vref +1.02 23 maximum output voltage on vhl (krfb) |vhl ? vref| with peak digital input 0.97 1.00 1.03 v 9 24 gain from vsab to vhl vfd = 1 4.9 5 5.1 v/v 25 gain from vsab to vhl vfd = 0 ? 0.0255 ? 0.025 ? 0.0245 v/v 26 % error of vlb voltage (for vlb equation, see am79r2xx/ am79d2251 technical reference ) ? 5+5% 27 capacitance load on vlb1 ? 2 120 pf 5
am79d2251 17 transmission and signaling specifications table 1. 0 dbm0 voltage definitions with unity gain in x, r, gx, gr, ax, and ar 28 capacitance load on xsb1 ? 2, xsc 400 pf 5 signal at digital interface transmit receive unit a-law digital mw or equivalent (0 dbm0) 0.5026 0.5026 vrms -law digital mw or equivalent (0 dbm0) 0.4987 0.4987 5,800 peak linear coded sine wave 0.5026 0.5025 no. item condition min typ max unit note 1 insertion loss a-d d-a a-d + d-a a-d + d-a input: 1014hz, ? 10dbm0 rg = ar = ax = gr = gx = 0 db, aisn, r, x, b and z filters disabled temperature = 70 c variation over temperature ? 0.25 ? 0.25 ? 0.15 ? 0.1 0 0 0 0 +0.25 +0.25 +0.015 +0.1 db 6 2 level set error (error between setting and actual value) a-d ax + gx d-a ar + gr ? 0.1 0.1 3 dr to dx gain in full digital loopback mode dr input: 1014 hz, ? 10 dbm0 rg=ar=ax=gr=gx=0 db, disn, r, x, b and z filters disabled ? 0.3 +0.3 4 idle channel noise, psophometric weighted (a-law) off-hook and on-hook ax = 0db ar = 0db a-d (pcm output) d-a (v out ) ? 69 ? 78 dbm0p 11 5 idle channel noise, c message weighted (-law) off-hook and on-hook ax = 0db ar = 0db a-d (pcm output) d-a (v out ) +19 +12 dbrnc0 11 6 coder offset decision value, xn a-d, input signal = 0v ? 7+7bits5 7 gx step size 0 gx < 12 db 0.1 db 5 8 gr step size ? 12 gr 0 db 0.1 5 9 psrr (vcc) image frequency input: 4.8 to 7.8 khz, 200 mv p-p measure 8000 hz-input frequency a-d d-a 37 37 5 10 disn gain accuracy gdisn = 0.9375 vin = 0 dbm0 gdisn = ? 0.9375 to 0.9375 ? 0.25 +0.25 db 2 11 end-to-end group delay 1014 hz; ? 10 dbmo b = z = 0; x = r = 1 525 s13, 12, 5 12 crosstalk tx to rx same channel rx to tx 0 dbm0 300 hz to 3400 hz 0 dbm0 300 hz to 3400 hz ? 75 ? 75 dbm0 no. item condition min typ max unit note
18 am79d2251 notes: 1. these tests are performed with the following load impedances: frequency < 12 khz ? longitudinal impedance = 500 ? ; metallic impedance = 300 ? frequency > 12 khz ? longitudinal impedance = 90 ? ; metallic impedance = 135 ? 2. not tested or partially tested in production. this parameter is guaranteed by characterization or correlation to other tests. 3. this parameter is tested at 1 khz in production. performance at other frequencies is guaranteed by characterization. 4. when the intelligent access voice chipset is in the anti-sat operating region, this parameter will be degraded. the exact degradation will depend on system design. 5. guaranteed by design. 6. overall 1.014 khz insertion loss error of the intelligent access voice chipset is guaranteed to be 0.34 db 7. these sbat, psrr specifications are valid only when the islic is used with the islac, which generates the anti-sat reference. since the anti-sat reference depends upon the battery voltage sensed by the vhb, vlb, and vpb pins of the islac, the psrr of the kit depends upon the amount of battery filtering provided by cb. 8. must meet at least one of these specifications. 9. these voltages are referred to vref 10. these limits refer to the 2-wire output of an ideal islic but reflect only the capabilities the islac. 11. when relative levels (dbm0) are used, the specification holds for any setting of (ax + gx) gain from 0 to 12 db or (ar + gr + rg) from 0 to ?12 db. 12. group delay spec valid only when channels 1?2 occupy consecutive slots in the frame. programming channels in non-consecutive timeslots adds 1 frame delay in the group delay measurements. 13. the group delay specification is defined as the sum of the minimum values of the group delays for transmit and the receive paths when the b, x, r, and z filters are disabled with null coefficients. see figure 15-3 for group delay distortion. 14. these limits reflect only the capabilities of the dual islac device. 13 crosstalk between channels tx or rx to tx tx or rx to rx 0 dbm0 1014 hz 1014 hz ? 76 ? 78 dbm0 no. item condition min typ max unit note
am79d2251 19 transmit and receive paths in this section, the transmit path is defined as the analog input to the islac device (vinn) to the pcm voice output of the islac a-law/ law speech compressor (see figure 7-1 in the am79r2xx/ am79d2251x technical reference ). the receive path is defined as the pcm voice input to the islac speech expander to the analog output of the islac device (voutn). all limits defined in this section are tested with b = 0, z = 0 and x = r = rg = 1. when rg is enabled, a gain of ? 6.02 db is added to the digital section of the receive path. when ar is enabled, a nominal gain of ? 6.02 db is added to the analog section of the receive path. when ax is enabled, a nominal gain of +6.02 db is added to the analog section of the transmit path. when relative levels (dbm0) are used in any of the following transmission characteristics, the specification holds for any setting of (ax + gx) gain from 0 to 12 db or (ar + gr) from 0 to ? 12 db. these transmission characteristics are valid for 0 to 70 c.
20 am79d2251 attenuation distortion the attenuation of the signal in either path is nominally independent of the frequency. the deviations from nominal attenuation will stay within the limits shown in figure 6. the reference frequency is 1014 hz and the signal level is ? 10 dbm0. figure 6. transmit and receive path attenuation vs. frequency minimum transmit attenuation at 60 hz is 24 db group delay distortion for either transmission path, the group delay distortion is within the limits shown in figure 7. the minimum value of the group delay is taken as the reference. the signal level should be ? 10 dbm0. figure 7. group delay distortion 3000 3400 2 0.6 0 dual islac specification 0.65 -0.125 0.125 600 300 200 0 3200 0.80 0.2 attenuation (db) receive path 1 frequency (hz) 0 500 600 1000 2600 2800 90 150 420 delay (s) dual islac specification (either path) frequency (hz)
am79d2251 21 single frequency distortion the output signal level, at any single frequency in the range of 300 to 3400 hz, other than that due to an applied 0 dbm0 sine wave signal with frequency f in the same frequency range, is less than ? 46 dbm0. with f swept between 0 to 300 hz and 3.4 to 12 khz, any generated output signals other than f are less than ? 28 dbm0. this specification is valid for either transmission path. intermodulation distortion two sine wave signals of different frequencies, f 1 and f 2 (not harmonically related) in the range 300 to 3400 hz and of equal levels in the range ? 4 to ? 21 dbm0, do not produce 2 f 1 ? f 2 products having a level greater than ? 42 db, relative to the level of the two input signals. a sine wave signal in the frequency band 300 to 3400 hz with input level ? 9 dbm0 and a 50 hz signal with input level ? 23 dbm0 does not produce intermodulation products exceeding a level of ? 56 dbm0. these specifications are valid for either transmission path.
22 am79d2251 gain linearity the gain deviation relative to the gain at ? 10 dbm0 is within the limits shown in figure 8 (a-law) and figure 9 (-law) for either transmission path when the input is a sine wave signal of 1014 hz. figure 8. a-law gain linearity with tone input (both paths) figure 9. -law gain linearity with tone input (both paths) 0.55 0.25 0 -0.25 -0.55 -1.5 -55 -50 -40 -10 +3 1.5 gain (db) input level (dbm0) 0 dual islac specification 0.45 0.25 0 -0.25 -0.45 -1.4 -55 -50 -37 -10 +3 1.4 gain (db) input level (dbm0) 0 dual islac specification
am79d2251 23 total distortion including quantizing distortion the signal to total distortion ratio will exceed the limits shown in figure 10 for either path when the input signal is a sine wave signal of frequency 1014 hz. figure 10. total distortion with tone input, both paths overload compression figure 11 shows the acceptable region of operation for input signal levels above the reference input power (0 dbm0). the conditions for this figure are: (1) 1 db < gx +12 db; (2) ? 12 db gr < ? 1 db; (3) digital voice output connected to digital voice input; and (4) measurement analog to analog. figure 11. a/a overload compression input level (dbm0) signal-to-total distortion (db) dual islac specification 0 -30 -40 -45 a a-law -law a 35.5db 35.5db b 35.5db 35.5db c 30db 31db d 25db 27db b c d fundamental output power (dbm0) fundamental input power (dbm0) 1 2 3 4 5 6 7 8 9 1234 56 789 region 2.6 acceptable
24 am79d2251 discrimination against out-of-band input signals when an out-of-band sine wave signal with frequency and level a is applied to the analog input, there may be frequency components below 4 khz at the digital output which are caused by the out-of-band signal. these components are at least the specified db level below the level of a signal at the same output originating from a 1014 hz sine wave signal with a level of a dbm0 also applied to the analog input. the minimum specifications are shown in the following table. frequency of out-of-band signal amplitude of out-of-band signal level below a 16.6 hz < f < 45 hz ? 25 dbm0 < a 0 dbm0 18 db 45 hz < f < 65 hz ? 25 dbm0 < a 0 dbm0 25 db 65 hz < f < 100 hz ? 25 dbm0 < a 0 dbm0 10 db 3400 hz < f < 4600 hz ? 25 dbm0 < a 0 dbm0 see figure 12 4600 hz < f < 100 khz ? 25 dbm0 < a 0 dbm0 32 db 0 ? 10 ? 20 ? 30 ? 40 ? 50 frequency (khz) 3.4 4.0 4.6 ? 32 db, ? 25 dbm0 < input < 0 dbm0 islac device specification level (db) 19256a-012 ? 28 dbm note: the attenuation of the waveform below amplitude a between 3400 hz and 4600 hz is given by the formula: attenuation (db) 14 14 4000 f ? () 1200 ------------------------- - sin ? = figure 12. discrimination against out-of-band signals
am79d2251 25 spurious out-of-band signals at the analog output with pcm code words representing a sine wave signal in the range of 300 hz to 3400 hz at a level of 0 dbm0 applied to the digital input, the level of the spurious out-of-band signals at the analog output is less than the limits shown below. with code words representing any sine wave signal in the range 3.4 khz to 4.0 khz at a level of 0 dbm0 applied to the digital input, the level of the signals at the analog output are below the limits in figure 13. the amplitude of the spurious out-of-band signals between 3400 hz and 4600 hz is given by the formula: frequency level 4.6 khz to 40 khz ? 32 dbm0 40 khz to 240 khz ? 46 dbm0 240 khz to 1 mhz ? 36 dbm0 a14 ? 14 f4000 ? () 1200 ---------------------------- dbm0 sin ? = 0 ? 10 ? 20 ? 30 ? 40 ? 50 ? 28 db ? 32 db islac device specification frequency (khz) 3.4 4.0 4.6 19256a-013 level (dbm0) figure 13. spurious out-of-band signals
26 am79d2251 switching characteristics pcm switching characteristics figure 14. pcm switching characteristics vcc = 3.3 v + 5%, agnd = dgnd = 0 v microprocessor interface min and max values are valid for all digital outputs with a 100 pf load, except dio,dxa, intl, and tsca which are valid with 150 pf loads. no. symbol parameter min typ max unit note 1t dcy data clock period 122 ns 2t dch data clock high pulse width 48 1 3t dcl data clock low pulse width 48 1 4t dcr rise time of clock 15 5t dcf fall time of clock 15 6t icss chip select setup time, input mode 30 t dcy ? 10 7t icsh chip select hold time, input mode 0 t dch ? 20 8t icsl chip select pulse width, input mode 8t dcy 9t icso chip select off time, input mode 1, 6 10 t ids input data setup time 25 5 11 t idh input data hold time 30 12 13 t ocss chip select setup time, output mode 30 t dcy ? 10 ns 14 t ocsh chip select hold time, output mode t dch ? 20 15 t ocsl chip select pulse width, output mode 8t dcy 16 t ocso chip select off time, output mode 1, 6 17 t odd output data turn on delay 50 18 t odh output data hold time 3 19 t odof output data turn off delay 50 20 t odc output data valid 0 50 21 t rst reset pulse width 50 s tbd tbd test points tbd tbd tbd tbd
am79d2251 27 pcm interface master clock for 2.048 mhz 100 ppm, 4.096 mhz 100 ppm, or 8.192 mhz 100 ppm operation: notes: 1. dclk may be stopped in the high or low state indefinitely without loss of information. when cs makes a transition to the high state, the last byte received will be interpreted by the microprocessor interface logic. 2. the pcm clock (pclk or mclk) frequency must be an integer multiple of the frame sync (fs) frequency with an accuracy of 100 ppm. this allowance includes any jitter that may occur between the pcm signals (fs, pclk) and mclk. the actual pclk rate is dependent on the number of channels allocated within a frame. the minimum clock frequency is 128 khz. a pclk of 1.544 mhz may be used for standard u.s. transmission systems. 3. tsca is delayed from fs by a typical value of n t pcy , where n is the value stored in the time/clock slot register. 4. t tso is defined as the time at which the output driver turns off. the actual delay time is dependent on the load circuitry. the maximum load capacitance on tsca is 150 pf and the minimum pull-up resistance is 360 ? . 5. the first data bit is enabled on the falling edge of cs or on the falling edge of dclk, whichever occurs last. 6. the islac device requires 2.0 s between sio operations. if the mpi is being accessed while the mclk (or pclk if combined with mclk) input is not active, a chip select off time of 20 s is required when accessing coefficient ram. no. symbol parameter min. typ max unit note 22 t pcy pcm clock period 0.122 7.8125 s 2 23 t pch pcm clock high pulse width 48 ns 24 t pcl pcm clock low pulse width 48 25 t pcf fall time of clock 15 26 t pcr rise time of clock 15 27 t fss fs setup time 30 t pcy ? 30 28 t fsh fs hold time 50 29 t tsd delay to tsca valid 5 80 3 30 t tso delay to tsca off 5 4 31 t dxd pcm data output delay 5 70 32 t dxh pcm data output hold time 5 70 33 t dxz pcm data output delay to high-z 10 70 34 t drs pcm data input setup time 25 35 t drh pcm data input hold time 5 36 t fst pcm or frame sync jitter time ? 97 97 no. symbol parameter min typ max unit no 37 t mcy period: 2.048 mhz period: 4.096 mhz period: 8.192 mhz 488.23 244.11 122.05 488.28 244.14 122.07 488.33 244.17 122.09 ns 2 38 t mcr rise time of clock 15 39 t mcf fall time of clock 15 40 t mch mclk high pulse width 48 41 t mcl mclk low pulse width 48
28 am79d2251 pcm switching waveforms figure 15. master clock timing figure 16. microprocessor interface (input mode) 38 41 40 39 v il v ih 37 data valid 1 5 v il dclk 9 4 cs data valid 11 dio 2 3 6 8 10 7 data valid v ih v il v ih
am79d2251 29 figure 17. microprocessor interface (output mode) figure 18. pcm highway timing for xe = 0 (transmit on negative pclk edge)) 16 15 dclk cs dio three-state three-state 13 14 19 20 18 17 data valid data valid data valid v oh v ol v il v ih time slot zero, clock slot zero 33 30 first bit pclk fs dxa first bit second bit v ol v oh tsca v ih v il v ih v il see note 4 26 24 23 28 29 31 32 27 22 25 34 35 dra
30 am79d2251 figure 19. pcm highway timing for xe = 1 (transmit on positive pclk edge) gci timing specifications notes: 1. the data clock (dcl) can be stopped in the high or low state without loss of information. 2. a temporary stoppage of dcl must not put the islac into a state in which it does not respond to a software reset command. 3. all frequency-dependent specifications are guaranteed for clock frequencies within 100 ppm from nominal. symbol signal parameter min typ max unit t r , t f dcl rise/fall time 60 ns t dcl dcl period, f dcl = 2048 khz f dcl = 4096 khz 478 239 498 249 t wh , t wl dcl pulse width 90 t r , t f fs rise/fall time 60 t sf fs setup time 70 t dcl ? 50 t hf fs hold time 50 t wfh fs high pulse width 130 t ddc du delay from dcl edge 100 t ddf du delay from fs edge 150 t sd dd data setup twh+20 t hd dd data hold 50 pclk fs first bit second bit v ih v il v ih v il 26 24 23 27 22 25 28 34 35 dra 33 30 first bit dxa v ol v oh tsca see note 4 31 32 29 time slot zero, clock slot zero
am79d2251 31 gci waveforms detail a t r dcl fs dcl** fs du dd bit 7 bit 6 dd, du ** timing diagram valid for f dcl = 2048 or 4096 khz t f t wh t dcl t wl t sf t hf t ddf t wfh t ddc t hd t sd
32 am79d2251 physical dimensions 44-pin plcc 44-pin tqfp top view seating plane .685 .695 .650 .656 pin 1 i.d. .685 .695 .650 .656 .026 .032 .050 ref .042 .056 .062 .083 .013 .021 .590 .630 .500 ref .009 .015 .165 .180 .090 .120 16-038-sq pl 044 da78 6-28-94 ae side view 1.00 ref. 1.20 max 11 ? 13 11 ? 13 0.80 bsc 44 1 0.95 1.05 11.80 12.20 9.80 10.20 11.80 12.20 9.80 10.20 0.30 0.45 16-038-pqt-2 pqt 44 7-11-95 ae
am79d2251 33 revision summary revision a to revision b revision a was a condensed version of the datasheet while revision b contains the full version. revision b to revision c page 13, linecard parts list, rows chlbi and chldi: switched the numbers in the ? va l u e s ? column. the contents of this document are provided in connection with advanced micro devices, inc. ("amd") products. amd makes no repre sentations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make c hanges to speci- fications and product descriptions at any time without notice. no license, whether express, implied, arising by estoppel or oth erwise, to any in- tellectual property rights is granted by this publication. except as set forth in amd ? s standard terms and conditions of sale, amd assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, th e implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. amd ? s products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant i nto the body, or in other applications intended to support or sustain life, or in any other application in which the failure of amd ? s product could create a situation where personal injury, death, or severe property or environmental damage may occur. amd reserves the right to discont inue or make changes to its products at any time without notice. ? 1999 advanced micro devices, inc. all rights reserved. trademarks amd, the amd logo and combinations thereof are trademarks of advanced micro devices, inc. intelligent access and winslac are trademarks of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies .
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